
The invention relates to an amplifier circuit with offset compensation, in particular for digital modulation devices. The amplifier circuit has a differential amplifier and a control circuit with a control switch which is controlled by an offset voltage of the differential amplifier and which feeds an offset compensation signal into the differential amplifier.
Offset voltages normally occur at the output in the case of integrated differential amplifiers. The offset voltages may, for example, be determined by manufacturing tolerances that may have a negative effect on the symmetry of the circuit configuration. Other possible causes for offset voltages at outputs of differential amplifiers are mismatching of the integrated components or, in the case of direct conversion receiver (DCR) architectures of radio-frequency receivers, self-combining effects.
In receiver paths of radio-frequency receivers, such as those used in large numbers in mobile radio applications, analog/digital converters are normally connected downstream of differential amplifiers or combiner stages, which may have DC voltage offsets at the output side, thereby enabling digital further processing of data or voice signals in the baseband. However, if the signal fed to the AD converters has a DC voltage offset, the converters, which have a limited dynamic range, may be overloaded.
It is known for DC voltage offsets to be compensated by providing a capacitive connection to the downstream stage. However, if the frequency of the user information signal is low, the connection capacitors required for integration are too large and too expensive.
A generic amplifier circuit with analog offset compensation of DC voltage offsets is known from Published, European Patent Application EP 0 693 823 A1. The offset voltage is fed therein via an operational amplifier to a capacitor that is provided externally. A comparison of the capacitor voltage with a reference voltage enables generation of compensation currents that counteract the offset voltage.
This known offset compensation presents the disadvantage that leakage currents may flow due to less than ideal conditions in the capacitor or the integrated circuit, whereby the voltage present on the capacitor is subject to temporal drift. This may distort the offset compensation. Consequently, the selected capacitor must not be too small. Furthermore, excessive charge or discharge currents may result in control instabilities.
It is accordingly an object of the invention to provide an amplifier circuit with offset compensation, in particular for digital modulation devices that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a drift-free offset compensation, which enables rapid adjustment, is implemented.
With the foregoing and other objects in view there is provided, in accordance with the invention, an amplifier circuit with offset compensation. The amplifier circuit contains a differential amplifier outputting an offset voltage, and a control circuit having a digital setting device connected to the differential amplifier. The control circuit receives and processes the offset voltage of the differential amplifier and feeds an offset compensation signal back to the differential amplifier.
The object is achieved according to the invention with an amplifier circuit of the aforementioned type, in which the control circuit has a digital setting device.
The implementation of the amplifier circuit with a digital setting device in the control circuit offers the advantage that, due to the elimination of an external storage capacitor and associated time constants, very fast, drift-free compensation of a DC voltage offset is possible. Furthermore, the compensation can be carried out very quickly, since the duration depends only on the response time of the differential amplifier.
Further advantages are offered by the facility for chip-internal integration of the digital setting device, thereby eliminating the need for a connection pin. Furthermore, in one circuit configuration, there is no need to take account of a reduction in leakage currents that could discharge the capacitor. The offset voltage can be fed to the digital setting device. An offset compensation signal, which can be fed into the differential amplifier, can be formed in the digital setting device.
In an advantageous embodiment of the present invention, a comparator is connected on the output side to the differential amplifier in order to provide the offset voltage sign.
In a further advantageous embodiment of the present invention, the setting device is connected to the comparator in order to supply the output voltage sign. This produces a particularly simple circuit configuration, since only the offset voltage sign, which may be binary-coded in one bit, is supplied to the digital setting device.
In a further advantageous embodiment of the present invention, the setting device has a setting or control unit with a downstream digital/analog converter.
In a further advantageous embodiment of the present invention, the setting unit and a digital/analog converter are connected to a word line in order to transmit a setting parameter.
In a further advantageous embodiment of the present invention, the setting unit has a register to store a digitally coded offset compensation value.
In a further advantageous embodiment of the present invention, the digital/analog converter has current sources. Compensation currents which can be fed to the differential amplifier and which counteract the offset voltage can thereby be generated.
In a further advantageous embodiment of the present invention, the comparator has a hysteresis which describes the dependence of the sign on the output side on the offset voltage on the input side, the hysteresis advantageously being smaller than the minimum offset voltage which is to be compensated. A sign, which may be binary-coded, can thereby be assigned in a reliable manner to each offset voltage present on the input side on the comparator. A logical 1, for example, can be allocated to a positive sign, and a logical 0 can be allocated to a negative sign. The logical level allocation can also be reversed.
Finally, in an advantageous embodiment of the present invention, the control circuit can have a control unit to form the offset compensation signal with what is known as the xe2x80x9csuccessive approximationxe2x80x9d method. In an analog/digital conversion according to the successive approximation method, starting with the most significant bit (MSB) and continuing through to the least significant bit (LSB), in each case one bit is set and a subsequent check is carried out to establish whether a sign change occurs in a comparison between a required value and an actual value. If so, the bit is withdrawn. If not, the bit remains set. In each case, the next lowest bit is subsequently set and a required value is again compared with an actual value. This successive approximation procedure is repeated until the lowest bit is also defined. Since, in the present configuration, the offset voltage sign can be derived from a differential signal, no required signal or reference signal is needed to form the sign.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an amplifier circuit with offset compensation, in particular for digital modulation devices, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.